Advance Technologies; Automate the World.Manual Rev. 2.01Revision Date: December 21, 2006Part No: 50-11106-101cPCI-7300A/PCI-7300A80MB Ultra-High S

vi Table of ContentsWarranty Policy ... 99

88 C/C++ Libraries5.24 _7300_DO_Timer@ Description This function is used to set the internal timer pacer for digital out-put. Timer pacer frequency =

C/C++ Libraries 895.25 _7300_Int_Timer@ Description This function is used to set Counter #2.@ SyntaxVisual C/C++ (Windows 95)int W_7300_Int_Timer (in

90 C/C++ Libraries5.26 _7300_Get_Sample@ Description For the language without pointer support such as Visual Basic,programmer can use this function to

C/C++ Libraries 915.27 _7300_Set_Sample@ Description For the language without pointer support such as Visual Basic,programmer can use this function t

92 C/C++ Libraries5.28 _7300_GetUnderrunStatus@ Description When you use _7300_DO_DMA_Start to output data, the outputdata is read from the FIFO on th

Appendix 93Appendix8254 Programmable Interval TimerNote: The material of this section is adopted from “Intel Micropro-cessor and Peripheral Handbook

94 AppendixControl Byte: (Base + 7, Base + 11)X SC1 & SC1 - Select Counter (Bit7 & Bit 6)X RL1 & RL0 - Select Read/Load operation (Bit 5 &

Appendix 95 2. The count of the BCD counter is from 0 up to 99,999.Mode DefinitionIn 8254, there are six different operating modes can be select

96 AppendixThe gate input when low, will force the output high. When thegate input goes high, the counter will start form the initial count.Thus, the

Appendix 97Mode 5: Hardware Triggered Strobe.The counter will start counting after the rising edge of the trig-ger input and will go low for one cloc

List of Tables viiList of TablesTable 2-1: Connector Pin Assignment ... 12Table 3-1: I/O Port Base Address ...

98 Appendix

Warranty Policy 99Warranty PolicyThank you for choosing ADLINK. To understand your rights andenjoy all the after-sales services we offer, please read

100 Warranty Policy3. Our repair service is not covered by ADLINK's guaranteein the following situations:X Damage caused by not following instruc

viii List of FiguresList of FiguresFigure 2-1: PCI-7300A Layout Diagram... 9Figure 2-2: cPCI-7300A Layout Diagram

Introduction 11 IntroductionThe cPCI/PCI-7300A is cPCI/PCI form factor ultra-high speed dig-ital I/O card, it consists of 32 digital input or output

2Introduction1.1 ApplicationsX Interface to high-speed peripheralsX High-speed data transfers from other computersX Automated test equipment (ATE)X El

Introduction 31.3 SpecificationsDigital I/O (DIO)X Numbers of Channel: 32 TTL compatible inputs and/or out-putsX Device: IDT 74FCT373X I/O Configurat

4IntroductionDMA Transfer count: X No limitation for chaining mode (scatter/gather) DMAMax. Transfer rate: X DO: 80M Bytes/sec: 32-bit output @ 20 MHz

Introduction 51.4 Software SupportADLINK provides versatile software drivers and packages forusers’ different approach to built-up a system. We not

6IntroductionDAQ-LVIEW PnP: LabVIEW® DriverDAQ-LVIEW PnP contains the VIs, which are used to interfacewith NI’s LabVIEW® software package. The DAQ-LVI

Installation 72 InstallationThis chapter describes how to install the cPCI/PCI-7300A. At first,the contents in the package and unpacking information

Copyright 2006 ADLINK TECHNOLOGY INC.All Rights Reserved. The information in this document is subject to change without priornotice in order to improv

8Installation2.2 UnpackingYour cPCI/PCI-7300A card contains sensitive electronic compo-nents that can be easily damaged by static electricity.The card

Installation 92.4 PCI-7300A's LayoutFigure 2-1: PCI-7300A Layout Diagram

10 InstallationFigure 2-2: cPCI-7300A Layout Diagram

Installation 112.5 Hardware Installation OutlinePCI configurationThe PCI cards (or CompactPCI cards) are equipped with plugand play PCI controller, i

12 Installation2.6 Connector Pin AssignmentThe PCI-7300A comes equipped with one 100-pin SCSI type con-nector (CN1) located on the rear mounting plate

Installation 1384 DITRIG CONTROL IDI TRIG – can be used to control the start of data acquisition in all DI modes.78…81 AUXDI3…0 DATA IAUX DI 3…0 – ca

14 InstallationFigure 2-3: CN1 Pin Assignment

Installation 152.7 Wiring and TerminationTransmission line effects and environment noise, particularly onclock and control lines, can lead to incorr

16 Installation2.8 Termination Board SupportingThe cPCI/PCI-7300A can be connected with two daughter boards:DIN-100S or DIN-502S. The functionality an

Registers 173RegistersIn this chapter, the registers’ format of the cPCI/PCI-7300A isdescribed. Please note that the registers’ map of the PCI-7300AR

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18 Registers3.1 I/O Port Base AddressThe registers of the cPCI/PCI-7300A are shown in Table 3.1. Thebase address of these registers is also assigned

Registers 19Legend:X DI_CSR: Digital input control & status registerX DO_SCR: Digital output control & status registerX AUX_DIO: Auxiliary di

20 Registers3.2 DI_CSR: DI Control & Status Register Digital input control and status checking is done by this register.Address: BASE + 00Attribut

Registers 21DI_EN (R/W) X 0: Disable digital inputsX 1: Enable digital inputsDI_FIFO_CLR (R/W) X 0: No effectX 1: Clear digital input FIFO. If both P

22 Registers3.3 DO_CSR: DO Control & Status RegisterDigital input control and status checking is done by this register.Address: BASE + 04Attribute

Registers 23DO_WAIT_TRIG (R/W) X 0: start output data immediatelyX 1: delay output data until DOTRIG is actived PB_TERM_OFF (R/W) X 0: PORTB terminat

24 Registers3.4 Auxiliary Digital I/O RegisterAuxiliary 4-bit digital inputs and 4-bit digital outputsAddress: BASE + 08 Attribute: READ/WRITEData For

Registers 253.5 INT_CSR: Interrupt Control and Status Register The interrupt of PCI-7300A is controlled and status is checkedthrough this register.

26 Registers3.6 DI_FIFO: DI FIFO direct access port The digital input FIFO data can be accessed through this portdirectly. Address: BASE + 0x10Attrib

Registers 273.7 DO_FIFO: DO external data FIFO direct access port The digital output FIFO data can be accessed through this portdirectly. Address: B

28 Registers3.8 FIFO_CR: FIFO almost empty/full register The register is used to control the FIFO programmable almostempty/full flag. Address: BASE +

Registers 293.9 POL_CNTRL: Control Signal Polarity Control Register The register is used to control the control signals’ polarity. Thecontrol signa

30 Registers3.10 PLX PCI-9080 DMA Control RegistersThe registers of bus-mastering DMA as well as the control andstatus registers of PCI-bus interrupts

Operation Theory 314 Operation TheoryThis chapter provides the detailed operation information for thecPCI/PCI-7300A, including I/O configuration, blo

32 Operation TheoryX DO0:output LSB, DO31:output MSB.X LSB: Least Significant Bit, MSB: Most Significant Bit4.2 Block DiagramFigure 4-1 shows the bloc

Operation Theory 334.3 Digital I/O Data FlowWhen applying digital input functions, the data will be sampled intothe input FIFO periodically as we con

34 Operation Theory4.4 Input FIFO and Output FIFODue to the data transfer rate between external devices and thecPCI/PCI-7300A is independent from that

Operation Theory 35do chaining mode DMA which will generate the desired pat-tern repetitively.4.5 Bus-mastering DMADigital I/O data transfer between

36 Operation Theorytransfer the maximum data size as they have on their systemmemory. However, if the data should be real-time saved to thehard-disk r

Operation Theory 374.6 Scatter/gather DMAThe PCI Bridge also supports the function of scatter/gather busmastering DMA, which helps the users to trans

Table of Contents iTable of ContentsTable of Contents... iList of Tables...

38 Operation Theory4.7 Clocking ModeThe data input to or output from the FIFO is operated in a specificrate. The specific sampling rate or the pacer r

Operation Theory 39tion of DI-ACK. If the external device follows the rule,there would be no data lost due to FIFO overrun.3. Handshaking: For the di

40 Operation Theory4.8 Starting ModeUsers can also control the starting mode of digital input and outputby external signals (DITRIG and DOTRIG) with t

Operation Theory 414.10 Digital Input Operation ModeDigital Input DMA in Internal Clock ModeThere are three sources to trigger digital input in the i

42 Operation TheoryThe operation flow is show as below: Note: When the DMA function of digital input starts, the input data will be stored in the FIF

Operation Theory 43than the on-board FIFO buffer time. The FIFO size is 16K sample, so it has 1.6 ms buffer time for 10MHz sampling rate if the FIFO

44 Operation TheoryThe operation flow is show as below: The followings are timing diagrams of the DI-REQ and the inputdata. The active edge of DI-REQ

Operation Theory 45Figure 4-8: DIREQ as input data strobe (Falling Edge Active)Note: From the timing diagram of external clock mode, the maxi-mum fr

46 Operation Theoryfer.The operations sequence of digital input with handshaking arelisted:1. Define the input configuration to be 32-bit, 16-bit or 8

Operation Theory 47The following figure shows the timing requirement of the hand-shaking mode digital input operation.Figure 4-9: DIREQ & DIACK H

ii Table of Contents3.10 ... PLX PCI-9080 DMA Control Registers 304 Operation Theory ...

48 Operation Theoryand remove the unnecessary processes in your applica-tion programs.3. When high-speed sampling frequency is applied, thelarger bloc

Operation Theory 494.11 Digital Output Operation ModeDigital Output DMA in Internal Clock ModeThere are three sources to trigger digital output: 20MH

50 Operation TheoryAs the data output in the internal clock mode, the DOREQ signalcould be use as the output strobe to indicate the output operationto

Operation Theory 51The operations sequence of digital output in handshaking modeare listed:1. Define the input configuration to be 32-bit, 16-bit or

52 Operation TheoryThe timing diagram of the DOREQ and DOACK in the DO hand-shaking mode is shown as follows:Figure 4-11: DOREQ & DOACK Handshakin

Operation Theory 53The operations sequence of digital output in burst handshakingmode are listed:1. Define the input configuration to be 32-bit, 16-b

54 Operation TheoryThe operation flow is show as below: Note: When the DMA function of digital output starts, the output data will transfer to the out

Operation Theory 55Pattern GeneratorThe digital data is output to the peripheral device periodicallybased on the clock signals occur at a constant ra

56 Operation Theory4.12 Auxiliary DIOThe cPCI/PCI-7300A also includes four auxiliary digital inputs andfour digital outputs, which can be applied to a

C/C++ Libraries 575 C/C++ LibrariesThis chapter describes the software library for operating this card.Only the functions in DOS library and Windows

Table of Contents iii@ Description ... 62@ Syntax ...

58 C/C++ Libraries5.2 Programming GuideNaming ConventionThe functions of the NuDAQ PCI cards or NuIPC CompactPCIcards’ software driver are using full

C/C++ Libraries 595.3 _7300_Initial@ DescriptionA PCI-7300A card is initialized according to the card number.Because the cPCI/PCI-7300A is PCI bus ar

60 C/C++ Librariesirq_no:system will give an available interrupt number to this cardautomatically.pci_master:TRUE: BIOS enabled PCI bus mastering

C/C++ Libraries 615.4 _7300_Close@ DescriptionClose a previously initialized PCI-7300A card.@ SyntaxVisual C/C++ (Windows 95)int W_7300_Close (int ca

62 C/C++ Libraries5.5 _7300_Configure@ DescriptionSet the port DI/O configuration, terminator control, and control sig-nal polarity for the PCI-7300A

C/C++ Libraries 63PAON_PBOFF: PORTA terminator ON, PORTB terminator OFFPAON_PBON: PORTA terminator ON, PORTB terminator ONNote: term_cntrl is used to

64 C/C++ Libraries5.6 _7300_DI_Mode@ DescriptionSet the clock mode and start mode for the PCI-7300A DI opera-tion.@ SyntaxVisual C/C++ (Windows 95)int

C/C++ Libraries 655.7 _7300_DO_Mode@ DescriptionSet the clock mode and start mode for the PCI-7300A DO opera-tion.@ SyntaxVisual C/C++ (Windows 95)in

66 C/C++ LibrariesDO_WAIT_BOTH: delay output data until DOTRIG is active and FIFO is not almost empty.fifo_threshold:programmable almost empty thresho

C/C++ Libraries 675.8 _7300_AUX_DI@ DescriptionRead data from auxiliary digital input port. You can get all 4 bitsinput data by using this function.@

iv Table of Contents@ Description ... 72@ Syntax ...

68 C/C++ Libraries5.9 _7300_AUX_DI_Channel@ DescriptionRead data from auxiliary digital input channel. There are 4 digitalinput channels on the PCI-73

C/C++ Libraries 695.10 _7300_AUX_DO@ DescriptionWrite data to auxiliary digital output port. There are 4 auxiliary dig-ital outputs on the PCI-7300A.

70 C/C++ Libraries5.11 _7300_AUX_DO_Channel@ DescriptionWrite data to auxiliary digital output channel (bit). There are 4 aux-iliary digital output ch

C/C++ Libraries 715.12 _7300_Alloc_DMA_Mem@ DescriptionContact Windows 95 system to allocate a memory for DMA trans-fer. This function is only availa

72 C/C++ Libraries5.13 _7300_Free_DMA_Mem@ DescriptionDeallocate a system DMA memory under the Windows 95 envi-ronment. This function is only availabl

C/C++ Libraries 735.14 _7300_DI_DMA_Start@ Description The function will perform digital input by DMA data transfer.It will take place in the backgro

74 C/C++ Librariesdata transfer continually tests if any data in the FIFO andthen blocks transfer, the system will continuously loopuntil the conditio

C/C++ Libraries 75@ Argumentcard_number:The card number of the PCI-7300A card.mode (DOS):CHAIN_DMA: chaining DMA mode. By using thescatter-gather cap

76 C/C++ LibrariesPCICardNotInitDMATransferNotAllowedInvalidDIOCountBufNotDWordAlignDMADscrBadAlign

C/C++ Libraries 775.15 _7300_DI_DMA_Status@ Description Since the _7300_DI_DMA_Start function is executed in back-ground, you can issue this function

Table of Contents v@ Argument ... 84@ Return Code ...

78 C/C++ Libraries5.16 _7300_DI_DMA_Abort@ Description This function is used to stop the DMA DI operation. After executingthis function, the DMA trans

C/C++ Libraries 795.17 _7300_GetOverrunStatus@ Description When you use _7300_DI_DMA_Start to input data, the input datais stored in the FIFO of PCI

80 C/C++ Libraries5.18 _7300_DO_DMA_Start@ Description The function will perform digital output N times with DMA datatransfer. It will takes place in

C/C++ Libraries 81count:For non-chaining mode, this is the total number of digitaloutput data in double-words (4-byte). The value of count can notexc

82 C/C++ Libraries5.19 _7300_DO_DMA_Status@ Description Since the _7300_DO_DMA_Start function is executed in back-ground, you can issue the function _

C/C++ Libraries 835.20 _7300_DO_DMA_Abort@ Description This function is used to stop the DMA DO operation. After execut-ing this function, the _7300_

84 C/C++ Libraries5.21 _7300_DO_PG_Start@ Description The function will perform pattern generation with the data stored inbuff_ptr. It will takes plac

C/C++ Libraries 85DMADscrBadAlign

86 C/C++ Libraries5.22 _7300_DO_PG_Stop@ Description This function is used to stop the pattern generation operation.After executing this function, the

C/C++ Libraries 875.23 _7300_DI_Timer@ Description This function is used to set the internal timer pacer for digital input.Timer pacer frequency = 10