Adlink cPCI-6525 Instrukcja Użytkownika

Advance Technologies; Automate the World.Manual Rev.: 0.10 preliminaryRevision Date: April 17, 2015Part No: 50-15101-1010cPCI-65256U CompactPCI® 3r

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Introduction 1cPCI-65251 Introduction1.1 OverviewThe cPCI-6525 is a 6U CompactPCI® processor blade in sin-gle-slot (4HP) width form factor featuring

2IntroductionThe cPCI-6525 supports operation in both a system slot and in aperipheral slot as a standalone blade. The cPCI-6525 is compliantwith the

Introduction 3cPCI-65251.2 FeaturesX 6U CompactPCI® processor blade in 4HP width form factorX Quad-core 3rd Generation Intel® Core™ i7-3615QE 2.3GHz,

4Introduction1.3 Block DiagramFigure 1-1: cPCI-6525 Functional Block DiagramFront Panel DMIJ1/J2 J3/J4/J5 PCIe x1PCIe x1 6x USB 2.0 3x SATA HDA RTC

Introduction 5cPCI-65251.4 Product ListProcessor BladeX cPCI-6525: 4HP width (single-slot) 6U CompactPCI Pro-cessor BladeRear Transition ModuleX cPCI

6Introduction1.5 Package Contents The cPCI-6525 is packaged with the following components. If anyof the items on the contents list are missing or dama

Specifications 7cPCI-65252 Specifications2.1 cPCI-6525 Blade SpecificationsCompactPCI® Standards• PICMG® 2.0 CompactPCI® Rev. 3.0• PICMG® 2.1 Hot Swa

8 SpecificationsSerial Ports Four16C550 serial ports• One DB-9 RS-232/422/485 serial port on front panel • Three serial ports routed to rear I/O throu

Specifications 9cPCI-6525Notes:1. The storage device limits the operational vibration. When appli-cation requires higher specification for anti-vibra

Revision HistoryRevision Release Date Description of Change(s)0.10 2015/04/17 Preliminary release

10 Specifications2.3 Power RequirementsIn order to guarantee a stable functionality of the system, it is rec-ommended to provide more power than the s

Specifications 11cPCI-6525Power ConsumptionThis section provides information on the power consumption of thecPCI-6525 when using Intel® Core™ i7 proc

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Functional Description 13cPCI-65253 Functional DescriptionThe following sections describe the cPCI-6525 features andfunctions.3.1 ProcessorsThe 3rd G

14 Functional DescriptionSupported TechnologiesX Intel® Virtualization Technology for Directed I/O (Intel® VT-d)X Intel® Virtualization Technology (In

Functional Description 15cPCI-65253.2 ChipsetThe cPCI-6525 incorporates the Intel® QM77 Platform ControllerHub (PCH).Intel® QM77 Platform Controller

16 Functional Description3.3 Intel® Turbo Boost TechnologyIntel Turbo Boost Technology is a feature that allows the processorto opportunistically and

Functional Description 17cPCI-65253.6 TPMThe cPCI-6525 is equipped with the Infineon ATMEL AT97SC3204Trusted Platform Module (TPM), a security contro

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Board Interfaces 19cPCI-65254 Board Interfaces4.1 Board Layout - FrontFigure 4-1: cPCI-6525 Board Layout - FrontBT2 Battery J1-J5 CompactPCI connecto

Preface iiicPCI-6525PrefaceCopyright 2015 ADLINK Technology Inc.This document contains proprietary information protected by copy-right. All rights ar

20 Board Interfaces4.2 Board Layout - BackFigure 4-2: cPCI-6525 Board Layout - BackSW8 RGB to front/rear switch SW11 GbE to front/rear switchSW_11SW_8

Board Interfaces 21cPCI-65254.3 cPCI-6525 Front PanelFigure 4-3: cPCI-6525 Front PanelStatus LEDsGeneral Purpose LEDsIn default mode, these eight LED

22 Board Interfaces4.4 Connector Pin AssignmentsSee “Board Layout - Front” on page 19 for connector locations.Front Panel ConnectorsGigabit Ethernet C

Board Interfaces 23cPCI-6525COM1 (CN7, RJ-45)COM1 RJ-45 to DB-9 CablePin # RS-232 RS-422 RS-4851 DCD# TX- Data-2RTS# — —3DSR# — —4TXD RX+ —5 RXD TX+

24 Board InterfacesUSB 3.0 Connectors (CN6, CN10, CN15)DVI-I ConnectorTable 4-1: DVI-I Connector Pin DefinitionPin # Signal Name1VCC2 Data-3 Data+4GN

Board Interfaces 25cPCI-6525Onboard ConnectorsSATA Connector on DB-LSATAPin # SignalS1 GNDS2 TX+S3 TX-S4 GNDS5 RX-S6 RX+S7 GNDP1 NCP2 NCP3 NCP4 GNDP5

26 Board InterfacesCFast Socket (on DB-CFAST)Pin # Signal NameGround S1SATA_TX-P S2SATA_TX-N S3Ground S4SATA_RX-N S5SATA_RX-P S6Ground S7CFast_CDI P1G

Board Interfaces 27cPCI-6525DB-LSATA/DB-CFAST Connector (CN9, CN22)Signal Name Pin # Pin # Signal NameGND 1 2 GNDGND 3 4 GNDGND 5 6 GNDGND 7 8 GNDGND

28 Board InterfacesCompactPCI J1 Connector Pin AssignmentPin Z A B C D E F25 GND +5V REQ64# ENUM# +3.3V +5V GND24 GND AD1 +5V V(I/O) AD0 ACK64# GND23

Board Interfaces 29cPCI-6525CompactPCI J2 Connector Pin AssignmentPin Z A B C D E F22 GND GA4 GA3 GA2 GA1 GA0 GND21 GND CLK6 GND NC NC NC GND20 GND C

iv PrefaceConventionsTake note of the following conventions used throughout thismanual to make sure that users perform certain tasks andinstructions p

30 Board InterfacesCompactPCI J3 Pin AssignmentPin Z A B C D E F19 GND P5V P5V P12V P5V P5V GND18 GND LAN4_TXD1+ LAN4_TXD0- GND LAN4_TXD2+ LAN4_TXD2-

Board Interfaces 31cPCI-6525CompactPCI J4 Connector Pin AssignmentPin Z A B C D E F25 GND NC PCIE_TXP15 GNDPLTRST_PCIEX16PCIE_WAKE-L GND24 GND GND PC

32 Board InterfacesCompactPCI J5 Pin AssignmentPin Z A B C D E F22 GND LAN2_TXDP0 LAN2_TXDN0 GND LAN2_TXDP2 LAN2_TXDN2 GND21 GND LAN2_TXDP1 LAN2_TXDN1

Board Interfaces 33cPCI-65254.5 Buttons, Switches and JumpersSee “cPCI-6525 Front Panel” on page 21 and “Board Layout -Front” on page 19 for switch l

34 Board InterfacesCOM1 Mode Switch (SW12)Switch SW12 sets the mode of the COM1 port on the front panel.IPMC Mode Switch (SW_MOD1)Switch SW_MOD1 is a

Board Interfaces 35cPCI-6525RGB to Front/Rear Switch (SW8)GbE to Front/Rear Switch (SW11)Pin# Status Description1OFFRGB to front (default)ONRGB to re

36 Board InterfacesReserved SwitchesSwitches SW_COMDEG1 and SW_IPMCDEG1 are reservedand their settings should not be altered unless instructed byADLIN

Checkpoints & Beep Codes 37cPCI-65255 Checkpoints & Beep Codes5.1 Checkpoint Ranges5.2 Standard CheckpointsSEC PhaseStatus Code Range Descri

38 Checkpoints & Beep CodesSEC Beep Codes NonePEI Phase0x08 North Bridge initialization after microcode loading 0x09 South Bridge initialization a

Checkpoints & Beep Codes 39cPCI-65250x1A Pre-memory South Bridge initialization (South Bridge module specific) 0x1B Pre-memory South Bridge initi

Table of Contents vcPCI-6525Table of ContentsRevision History... iiPreface...

40 Checkpoints & Beep Codes0x3B Post-Memory South Bridge initialization is started 0x3C Post-Memory South Bridge initialization (South Bridge modu

Checkpoints & Beep Codes 41cPCI-65250xE3 OS S3 wake vector call 0xE4-0xE7 Reserved for future AMI progress codes S3 Resume Error Codes 0xE8 S3

42 Checkpoints & Beep CodesPEI Beep CodesDXE Phase# of Beeps Description 1 Memory not Installed 1Memory was installed twice (InstallPeiMemory ro

Checkpoints & Beep Codes 43cPCI-65250x6F North Bridge DXE initialization (North Bridge module specific) 0x70 South Bridge DXE initialization is

44 Checkpoints & Beep Codes0xA0 IDE initialization is started 0xA1 IDE Reset 0xA2 IDE Detect 0xA3 IDE Enable 0xA4 SCSI initialization is started

Checkpoints & Beep Codes 45cPCI-6525DXE Beep Codes0xD3 Some of the Architectural Protocols are not available 0xD4 PCI resource allocation error.

46 Checkpoints & Beep CodesACPI/ASL Checkpoints5.3 OEM-Reserved Checkpoint RangesStatus Code Description 0x01 System is entering S1 sleep state

Important Safety Instructions 47cPCI-6525Important Safety InstructionsFor user safety, please read and follow all instructions,WARNINGS, CAUTIONS, a

48 Important Safety InstructionsX Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel.A Lithium-type battery

Getting Service 49cPCI-6525Getting ServiceContact us should you require any service or assistance. ADLINK Technology, Inc. Address: 9F, No.166 Jia

vi Table of Contents4.3 cPCI-6525 Front Panel ... 214.4 Connector Pin Assignments...

50 Getting ServiceADLINK Technology, Inc. (French Liaison Office) Address: 6 allée de Londres, Immeuble Ceylan 91940 Les Ulis, France Tel: +33

List of Figures viicPCI-6525List of FiguresFigure 1-1: cPCI-6525 Functional Block Diagram... 4Figure 4-1: cPCI-6525 Board

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List of Tables ixcPCI-6525List of TablesTable 2-1: cPCI-6525 Blade Specifications .......... 7Table 2-2: cPCI-6525 I/O