Adlink DAQe-2502 Instrukcja Użytkownika Strona 1

Advance Technologies; Automate the World.Manual Rev. 2.01Revision Date: March 19, 2006Part No: 50-11221-2000NuDAQ-2500 SeriesHigh Performance Analo

iv List of FiguresList of FiguresFigure 1-1: DAQ-/DAQe-/PXI-2502/2501 Block Diagram ... 7Figure 2-1: DAQe-2502/2501 Card Layout ...

Introduction 11 IntroductionThe NuDAQ-2500 Series features the DAQ-/DAQe-/PXI-2502/2501 advanced analog output card based on the 32-bit PCI/PCIExpres

2IntroductionX System Synchronization Interface (SSI)X A/D and D/A fully auto-calibrationX Built-in programmable D/A external reference voltage com-pe

Introduction 31.3 SpecificationsAnalog Output (AO)X Channels:Z DAQ-/DAQe-/PXI-2501: 4-CHZ DAQ-/DAQe-/PXI-2502: 8-CHX DA converter: AD7945X Maximum up

4IntroductionAnalog Input (AI)X Channels:Z DAQ-/PXI-2502: 4 single-endedZ DAQ-/PXI-2501: 8 single-endedX AD converter: LTC1416X Max sampling rate: 400

Introduction 5General Purpose Digital I/O (G. P. DIO)X Channels: 24 programmable input/outputX Compatibility: TTL/CMOSX Input voltage: Z Logic Low: V

6IntroductionSystem Synchronous Interface (SSI)X Trigger lines: 7CalibrationX Recommended warm-up time: 15 minutesX Onboard reference: 5.0 VX Temperat

Introduction 71.4 Block DiagramFigure 1-1: DAQ-/DAQe-/PXI-2502/2501 Block Diagram

8Introduction1.5 Software SupportADLINK provides versatile software drivers and packages forusers’ different approach to building up a system. ADLINK

Introduction 9DAQ-LVIEW PnP: LabVIEW DriverDAQ-LVIEW PnP contains the VIs, which are used to interfacewith NI’s LabVIEW software package. The DAQ-LVI

Copyright 2007 ADLINK TECHNOLOGY INC.All Rights Reserved. The information in this document is subject to change without priornotice in order to improv

10 Introduction

Installation 112 InstallationThis chapter describes how to install the DAQ-/DAQe-/PXI-2502/2501 card. The contents of the package and unpacking infor

12 Installation2.2 UnpackingYour DAQ-/DAQe-/PXI-2502/2501 card contains electro-staticsensitive components that can be easily be damaged by staticelec

Installation 132.3 Card LayoutDAQe-2502/2501Figure 2-1: DAQe-2502/2501 Card Layout

14 InstallationDAQ-2502/2501Figure 2-2: DAQ-2502/2501 Card Layout

Installation 15DPXI-2501/2502Figure 2-3: DAQ-2502/2501 Card Layout

16 Installation2.4 PCI ConfigurationPlug and PlayWith support for plug and play, the card requests an interrupt num-ber via its PCI controller. The sy

Signal Connections 173 Signal ConnectionsThis chapter describes DAQ-/DAQe-/PXI-2502/2501 card connec-tors and the signal connection between the DAQ-/

18 Signal ConnectionsAO_0 1 35 AGNDAO_1 2 36 AGNDAO_2 3 37 AGNDAO_3 4 38 AGNDAOEXTREF_A/AI_0 5 39 AGNDAI_1 6 40 AGNDEXTATRIG/AI_2 7 41 AGNDAOEX

Signal Connections 19Legend:*PIO means Programmable Input/OutputPin # Signal Name Reference Direction Description1~4 AO_<0..3> AGND OutputVolta

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20 Signal Connections

Operation Theory 214 Operation TheoryThe operation theories of the DAQ-/DAQe-/PXI-2502/2501 cardare described in this chapter. The functions include

22 Operation TheoryAD Data FormatThe data format of the acquired 14-bit A/D data is coded in 2’scomplement. Table 4-1 and Table 4-2 lists the valid in

Operation Theory 23Acquisition ModesSoftware PollingThis is the easiest way to acquire a single A/D data. The A/Dconverter starts one conversion when

24 Operation TheoryScan Timing and ProcedureThere are four counters that need to be specified prior to program-mable scans. Refer to Table 4-4 for det

Operation Theory 25The relationship between counters and acquisition timing is illus-trated in Figure 4-1.Figure 4-1: Scan TimingNOTE The maximum A/D

26 Operation TheoryTrigger ModesPost-Trigger AcquisitionUse post-trigger acquisition when you want to perform scans rightafter a trigger signal. The n

Operation Theory 27Delay Trigger AcquisitionUse delay trigger when you want to delay the scan after a trig-ger signal. The delay time is determined b

28 Operation TheoryPost-Trigger or Delay-trigger Acquisition with RetriggerUse post-trigger or delay-trigger acquisition with retrigger whenyou want t

Operation Theory 29Bus-mastering DMA Data TransferBus Mastering DMA ModePCI bus-mastering DMA is necessary for high speed DAQ inorder to utilize the

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30 Operation Theorygather function, including some sample programs in theADLINK All-in-One CD.Figure 4-5: Scatter/gather DMA

Operation Theory 314.2 D/A ConversionThe DAQ-/DAQe-/PXI-2502/2501 card offers flexible and versatileanalog output scheme to fit your complex field ap

32 Operation TheoryHardware-Controlled Waveform GenerationFIFO is a hardware first-in first-out data queue that holds tempo-rary digital codes for D/A

Operation Theory 33Data Format in FIFO and MappingWith hardware-based waveform generation, D/A conversions areupdated automatically by CPLD rather th

34 Operation TheoryUsing DACs’ Multiplying CharacteristicThe D/A reference selection let you fully utilize the multiplyingcharacteristics of the DACs.

Operation Theory 35Waveform GenerationThis method is suitable for applications that need to generatewaveforms at a precise and fixed rate. Various pr

36 Operation TheoryWaveform Generation TimingSix counters interact with the waveform to generate differentDAWR timing, thus forming different waveform

Operation Theory 37Figure 4-8: Typical D/A Timing of Waveform Generation(Assuming the data in the data buffer are 2V, 4V, -4V, 0V)

38 Operation TheoryTrigger ModesPost-Trigger GenerationUse post-trigger generation when you want to generate wave-form right after a trigger signal. T

Operation Theory 39Delay-Trigger GenerationUse delay-trigger when you want to delay the waveform gener-ation after the trigger signal. The delay time

Using this manual1.1 Audience and scopeThis manual guides you when using ADLINK NuDAQ-2500 Seriescard. The card’s hardware, signal connections, and ca

40 Operation TheoryPost-Trigger or Delay-Trigger with RetriggerUse post-trigger or delay-trigger with retrigger when you wantto generate multiple wave

Operation Theory 41Iterative Waveform GenerationYou can set the IC_counter to generate iterative waveforms, nomatter which trigger mode is used. The

42 Operation TheoryWhen IC_counter is disabled, the waveform generation does notstop until a stop trigger is asserted. For Stop Mode, refer to thenext

Operation Theory 43Stop ModesYou may stop waveform generation while it is still in progress,either by hardware or software trigger. The stop trigger

44 Operation TheoryFigure 4-15: Stop Mode IIStop Mode IIIAfter a mode III stop trigger is asserted, the waveform genera-tion continues until the itera

Operation Theory 454.3 General Purpose Digital I/OThe DAQ-/DAQe-/PXI-2502/2501 card provides a 24-line general-purpose digital I/O (GPIO) via the 82

46 Operation Theory4.4 General Purpose Timer/Counter OperationTwo independent 16-bit up/down timer/counter are embedded inFPGA firmware for user appli

Operation Theory 47General Purpose Timer/Counter ModesEight programmable timer/counter modes are provided. All modesstart operations following the so

48 Operation TheoryFigure 4-18: Mode2 OperationMode3: Single Pulse-width MeasurementThe counter counts the pulse-width of the signal onGPTC_GATE in te

Operation Theory 49Mode4: Single Gated Pulse GenerationThis mode generates a single pulse with programmable delayand programmable pulse-width followi

1.3 ConventionsTake note of the following conventions used throughout the man-ual to make sure that you perform certain tasks and instructionsproperly

50 Operation TheoryMode6: Re-triggered Single Pulse GenerationThis mode is similar to mode 5 except that the counter gener-ates a pulse following ever

Operation Theory 51Mode8: Continuous Gated Pulse GenerationThis mode generates periodic pulses with programmable pulseinterval and pulse-width follow

52 Operation Theory4.5 Trigger SourcesThe DAQ-/DAQe-/PXI-2502/2501 card provides flexible triggerselections. In addition to software trigger, the DAQ-

Operation Theory 53The trigger signal asserts when an analog trigger condition is met.There are five analog trigger conditions in DAQ-/DAQe-/PXI-2502

54 Operation TheoryAbove-High Analog Trigger ConditionFigure 4-27 shows the above-high analog trigger condition, thetrigger signal asserts when the in

Operation Theory 55High-Hysteresis Analog Trigger ConditionFigure 4-29 shows the high-hysteresis analog trigger condition.The trigger signal asserts

56 Operation Theory4.6 Timing SignalsIn order to meet the requirements for user-specific timing or syn-chronizing multiple boards, the DAQ-/DAQe-/PXI-

Operation Theory 57System Synchronization InterfaceSSI uses bi-directional I/O to provide flexible connections betweenboards. You can choose each of

58 Operation Theory

Calibration 595 CalibrationThis chapter introduces the calibration process to minimize ADmeasurement errors and DA output errors.5.1 Loading Calibrat

Table of Contents iTable of ContentsTable of Contents... iList of Tables...

60 Calibration5.2 Auto-calibrationThrough the DAQ-/DAQe-/PXI-2502/2501 card auto-calibrationfeature, the calibration software measures and corrects al

Appendix 61AppendixWaveform Generation DemonstrationCombined with six counters, selectable trigger sources, externalreference sources, and time base,

62 AppendixIterative Generation w. Intermediate SpaceUtilize DLY2_counter to separate consecutive waveform generations in iterative generation mode. I

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64 Warranty Policy3. Our repair service is not covered by ADLINK's guaranteein the following situations:X Damage caused by not following instruct

ii Table of Contents3 Signal Connections ..... 173.1 Connectors Pin Assignment...

List of Tables iiiList of TablesTable 3-1: VHDCI-type (68-pin) Connector Pin Assignment ... 18Table 3-2: VHDCI-type (68-pin) Connector Legend ..